pub struct PciePort {
device_id: u16,
debug_label: String,
preferred_address: Option<PciAddress>,
pci_address: Option<PciAddress>,
bus_range: PciBridgeBusRange,
pcie_host: Option<PcieHostPort>,
pcie_config: Arc<Mutex<PcieConfig>>,
pm_config: Arc<Mutex<PmConfig>>,
msi_config: Option<Arc<Mutex<MsiConfig>>>,
root_cap: Arc<Mutex<PcieRootCap>>,
port_type: PcieDevicePortType,
prepare_hotplug: bool,
}
Fields§
§device_id: u16
§debug_label: String
§preferred_address: Option<PciAddress>
§pci_address: Option<PciAddress>
§bus_range: PciBridgeBusRange
§pcie_host: Option<PcieHostPort>
§pcie_config: Arc<Mutex<PcieConfig>>
§pm_config: Arc<Mutex<PmConfig>>
§msi_config: Option<Arc<Mutex<MsiConfig>>>
§root_cap: Arc<Mutex<PcieRootCap>>
§port_type: PcieDevicePortType
§prepare_hotplug: bool
Implementations§
source§impl PciePort
impl PciePort
sourcepub fn new(
device_id: u16,
debug_label: String,
primary_bus_num: u8,
secondary_bus_num: u8,
slot_implemented: bool,
port_type: PcieDevicePortType
) -> Self
pub fn new( device_id: u16, debug_label: String, primary_bus_num: u8, secondary_bus_num: u8, slot_implemented: bool, port_type: PcieDevicePortType ) -> Self
Constructs a new PCIE port
pub fn new_from_host( pcie_host: PcieHostPort, slot_implemented: bool, port_type: PcieDevicePortType ) -> Result<Self, PciDeviceError>
pub fn get_device_id(&self) -> u16
pub fn get_address(&self) -> Option<PciAddress>
pub fn debug_label(&self) -> String
pub fn preferred_address(&self) -> Option<PciAddress>
pub fn allocate_address( &mut self, resources: &mut SystemAllocator ) -> Result<PciAddress, PciDeviceError>
pub fn read_config(&self, reg_idx: usize, data: &mut u32)
pub fn write_config(&mut self, reg_idx: usize, offset: u64, data: &[u8])
pub fn handle_cap_write_result(&mut self, res: Box<dyn PciCapConfigWriteResult>)
pub fn get_caps( &self ) -> Vec<(Box<dyn PciCapability>, Option<Box<dyn PciCapConfig>>)>
pub fn get_bus_range(&self) -> Option<PciBridgeBusRange>
pub fn get_bridge_window_size(&self) -> (u64, u64)
pub fn get_slot_control(&self) -> u16
pub fn clone_interrupt(&mut self, msi_config: Arc<Mutex<MsiConfig>>)
pub fn hotplug_implemented(&self) -> bool
pub fn inject_pme(&mut self, requester_id: u16)
sourcepub fn is_hpc_pending(&self) -> bool
pub fn is_hpc_pending(&self) -> bool
Has command completion pending.
sourcepub fn set_hpc_sender(&mut self, event: Event)
pub fn set_hpc_sender(&mut self, event: Event)
Sets a sender for hot plug or unplug complete.
pub fn trigger_hp_or_pme_interrupt(&mut self)
pub fn is_host(&self) -> bool
sourcepub fn is_hotplug_ready(&self) -> bool
pub fn is_hotplug_ready(&self) -> bool
Checks if the slot is enabled by guest and ready for hotplug events.
sourcepub fn get_ready_notification(&mut self) -> Result<Event, PciDeviceError>
pub fn get_ready_notification(&mut self) -> Result<Event, PciDeviceError>
Gets a notification when the port is ready for hotplug. If the port is already ready, then the notification event is triggerred immediately.
pub fn hot_unplug(&mut self)
pub fn is_match(&self, host_addr: PciAddress) -> Option<u8>
pub fn removed_downstream_valid(&self) -> bool
pub fn mask_slot_status(&mut self, mask: u16)
pub fn set_slot_status(&mut self, flag: u16)
pub fn should_trigger_pme(&mut self) -> bool
pub fn prepare_hotplug(&mut self)
Auto Trait Implementations§
impl RefUnwindSafe for PciePort
impl Send for PciePort
impl Sync for PciePort
impl Unpin for PciePort
impl UnwindSafe for PciePort
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
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§impl<T> Downcast for Twhere
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