Struct devices::pci::pm::PmConfig

pub struct PmConfig {
    power_control_status: u16,
    cap_mapping: Option<PciCapMapping>,
}

Fields

power_control_status: u16

cap_mapping: Option<PciCapMapping>

Implementations

impl PmConfig

pub fn new(no_soft_reset: bool) -> Self

pub fn read(&self, data: &mut u32)

pub fn write(&mut self, offset: u64, data: &[u8])

pub fn should_trigger_pme(&mut self) -> bool

If device is in D3 and PME is enabled, set PME status, then device could inject a pme interrupt into guest

pub fn get_power_status(&self) -> PciDevicePower

Get device power status

Trait Implementations

impl PciCapConfig for PmConfig

fn read_mask(&self) -> &'static [u32]

Returns the read mask used by read_reg.

fn read_reg(&self, reg_idx: usize) -> u32

Reads a 32bit register from the capability. Only the bits set in the read mask will be used, while the rest of the bits will be taken from the PciConfiguration’s register data. reg_idx - index into the capability

fn write_reg( &mut self, reg_idx: usize, offset: u64, data: &[u8] ) -> Option<Box<dyn PciCapConfigWriteResult>>

Writes data to the capability. reg_idx - index into PciConfiguration.registers. offset - PciConfiguration.registers is in unit of DWord, offset define byte offset in the DWord. data - The data to write.

fn set_cap_mapping(&mut self, mapping: PciCapMapping)

Used to pass the mmio region for the capability to the implementation. If any external events update the capability’s registers, then PciCapMapping.set_reg must be called to make the changes visible to the guest.

fn num_regs(&self) -> usize