Module hypervisor::x86_64

source ·

Structs§

  • CpuConfigX86_64
    Hold the CPU feature configurations that are needed to setup a vCPU.
  • CpuId
    A container for the list of cpu id entries for the hypervisor and underlying cpu.
  • CpuIdEntry
    A CpuId Entry contains supported feature information for the given processor. This can be modified by the hypervisor to pass additional information to the guest kernel about the hypervisor or vm. Information is returned in the eax, ebx, ecx and edx registers by the cpu for a given function and index/subfunction (passed into the cpu via the eax and ecx register respectively).
  • DebugRegs
    State of a VCPU’s debug registers.
  • DescriptorTable
    State of a global descriptor table or interrupt descriptor table.
  • Fpu
    State of a VCPU’s floating point unit.
  • FpuReg
    x87 80-bit floating point value.
  • IoapicRedirectionTableEntry
    Represents a IOAPIC redirection table entry.
  • IoapicState
    Represents the state of the IOAPIC.
  • LapicState
    The LapicState represents the state of an x86 CPU’s Local APIC. The Local APIC consists of 64 128-bit registers, but only the first 32-bits of each register can be used, so this structure only stores the first 32-bits of each register.
  • MsiAddressMessage
  • MsiDataMessage
  • PicState
    Represents the state of the PIC.
  • PitChannelState
    The PitChannelState represents the state of one of the PIT’s three counters.
  • PitState
    The PitState represents the state of the PIT (aka the Programmable Interval Timer). The state is simply the state of it’s three channels.
  • Regs
    State of a VCPU’s general purpose registers.
  • Segment
    State of a memory segment.
  • Sregs
    State of a VCPU’s special registers.
  • VcpuInitX86_64
    Initial state for x86_64 VCPUs.
  • VcpuSnapshot
    x86 specific vCPU snapshot.
  • Xsave
    State of the VCPU’s x87 FPU, MMX, XMM, YMM registers. May contain more state depending on enabled extensions.

Enums§

  • CpuHybridType
    The hybrid type for intel hybrid CPU.
  • DeliveryMode
  • DeliveryStatus
  • DestinationMode
  • Level
    The level of a level-triggered interrupt: asserted or deasserted.
  • PicInitState
  • PicSelect
  • PitRWMode
    The PitRWMode enum represents the access mode of a PIT channel. Reads and writes to the Pit happen over Port-mapped I/O, which happens one byte at a time, but the count values and latch values are two bytes. So the access mode controls which of the two bytes will be read when.
  • PitRWState
    The PitRWState enum represents the state of reading to or writing from a channel. This is related to the PitRWMode, it mainly gives more detail about the state of the channel with respect to PitRWMode::Both.
  • TriggerMode

Constants§

Traits§

  • HypervisorX86_64
    A trait for managing cpuids for an x86_64 hypervisor and for checking its capabilities.
  • VcpuX86_64
    A wrapper around creating and using a VCPU on x86_64.
  • VmX86_64
    A wrapper for using a VM on x86_64 and getting/setting its state.

Functions§

Type Aliases§