Enum hypervisor::VcpuExit

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pub enum VcpuExit {

Show 29 variants    Io,
    Mmio,
    IoapicEoi {
        vector: u8,
    },
    Exception,
    Hypercall,
    Debug,
    Hlt,
    IrqWindowOpen,
    Shutdown(Result<(), VcpuShutdownError>),
    FailEntry {
        hardware_entry_failure_reason: u64,
    },
    Intr,
    SetTpr,
    TprAccess,
    InternalError,
    SystemEventShutdown,
    SystemEventReset,
    SystemEventCrash,
    InvalidVpRegister,
    UnsupportedFeature,
    Canceled,
    UnrecoverableException,
    MsrAccess,
    Cpuid {
        entry: CpuIdEntry,
    },
    RdTsc,
    ApicSmiTrap,
    ApicInitSipiTrap,
    BusLock,
    Sbi {
        extension_id: u64,
        function_id: u64,
        args: [u64; 6],
    },
    RiscvCsr {
        csr_num: u64,
        new_value: u64,
        write_mask: u64,
        ret_value: u64,
    },

}
Expand description

A reason why a VCPU exited. One of these returns every time Vcpu::run is called.

Variants§

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Io

An io instruction needs to be emulated. vcpu handle_io should be called to handle the io operation

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Mmio

A mmio instruction needs to be emulated. vcpu handle_mmio should be called to handle the mmio operation

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IoapicEoi

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§vector: u8
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Exception

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Hypercall

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Debug

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Hlt

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IrqWindowOpen

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Shutdown(Result<(), VcpuShutdownError>)

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FailEntry

Fields

§hardware_entry_failure_reason: u64
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Intr

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SetTpr

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TprAccess

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InternalError

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SystemEventShutdown

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SystemEventReset

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SystemEventCrash

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InvalidVpRegister

An invalid vcpu register was set while running.

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UnsupportedFeature

incorrect setup for vcpu requiring an unsupported feature

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Canceled

vcpu run was user cancelled

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UnrecoverableException

an unrecoverable exception was encountered (different from Exception)

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MsrAccess

vcpu stopped due to an msr access.

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Cpuid

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§entry: CpuIdEntry

vcpu stopped due to a cpuid request.

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RdTsc

vcpu stopped due to calling rdtsc

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ApicSmiTrap

vcpu stopped for an apic smi trap

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ApicInitSipiTrap

vcpu stopped due to an apic trap

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BusLock

vcpu stoppted due to bus lock

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Sbi

Fields

§extension_id: u64
§function_id: u64
§args: [u64; 6]

Riscv supervisor call.

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RiscvCsr

Fields

§csr_num: u64
§new_value: u64
§write_mask: u64
§ret_value: u64

Emulate CSR access from guest.

Trait Implementations§

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impl Clone for VcpuExit

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fn clone(&self) -> VcpuExit

Returns a copy of the value. Read more
1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for VcpuExit

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Copy for VcpuExit

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where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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Mutably borrows from an owned value. Read more
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fn into_any(self: Box<T>) -> Box<dyn Any>

Convert Box<dyn Trait> (where Trait: Downcast) to Box<dyn Any>. Box<dyn Any> can then be further downcast into Box<ConcreteType> where ConcreteType implements Trait.
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fn into_any_rc(self: Rc<T>) -> Rc<dyn Any>

Convert Rc<Trait> (where Trait: Downcast) to Rc<Any>. Rc<Any> can then be further downcast into Rc<ConcreteType> where ConcreteType implements Trait.
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Convert &Trait (where Trait: Downcast) to &Any. This is needed since Rust cannot generate &Any’s vtable from &Trait’s.
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Convert &mut Trait (where Trait: Downcast) to &Any. This is needed since Rust cannot generate &mut Any’s vtable from &mut Trait’s.
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where T: Any + Send + Sync,

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fn into_any_arc(self: Arc<T>) -> Arc<dyn Any + Send + Sync>

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> ToOwned for T
where T: Clone,

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type Owned = T

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impl<T, U> TryFrom<U> for T
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type Error = Infallible

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Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

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Performs the conversion.