hypervisor
0.1.0
In hypervisor::x86_64
Structs
CpuConfigX86_64
CpuId
CpuIdEntry
DebugRegs
DescriptorTable
Fpu
FpuReg
IoapicRedirectionTableEntry
IoapicState
LapicState
MsiAddressMessage
MsiDataMessage
PicState
PitChannelState
PitState
Regs
Segment
Sregs
VcpuInitX86_64
VcpuSnapshot
Xsave
Enums
CpuHybridType
DeliveryMode
DeliveryStatus
DestinationMode
Level
PicInitState
PicSelect
PitRWMode
PitRWState
TriggerMode
Constants
MSR_F15H_PERF_CTL0
MSR_F15H_PERF_CTL1
MSR_F15H_PERF_CTL2
MSR_F15H_PERF_CTL3
MSR_F15H_PERF_CTL4
MSR_F15H_PERF_CTL5
MSR_F15H_PERF_CTR0
MSR_F15H_PERF_CTR1
MSR_F15H_PERF_CTR2
MSR_F15H_PERF_CTR3
MSR_F15H_PERF_CTR4
MSR_F15H_PERF_CTR5
MSR_IA32_PERF_CAPABILITIES
MSR_IA32_TSC
NUM_IOAPIC_PINS
Traits
HypervisorX86_64
VcpuX86_64
VmX86_64
Functions
host_phys_addr_bits
Type Aliases
LapicRegister
?
Constant
hypervisor
::
x86_64
::
MSR_IA32_TSC
source
·
[
−
]
pub const MSR_IA32_TSC:
u32
= 0x00000010;