Configures the GDT, IDT, and segment registers for long mode.
Configures the GDT, IDT, and segment registers for 32-bit protected mode with paging disabled.
Returns the count of variable MTRR entries specified by the list of msrs
.
Returns true
if the given MSR id
is a MTRR entry.
Returns the default value of MSRs at reset.
Configure Model specific registers for long (64-bit) mode.
Returns a set of MSRs containing the MTRR configuration.
Configures the system page tables and control registers for long mode with paging.
Prepares identity mapping for the low 4GB memory.
Returns the number of variable MTRR entries supported by vcpu
.