Module pci_root

Structs§

PciConfigIo: Emulates PCI configuration access mechanism #1 (I/O ports 0xcf8 and 0xcfc).
PciConfigIoSerializable 🔒
PciConfigMmio: Emulates PCI memory-mapped configuration access mechanism.
PciConfigMmioSerializable 🔒
PciRoot: Emulates the PCI Root bridge.
PciRootConfiguration 🔒
PciRootMmioState 🔒
PciRootSerializable 🔒: Used to serialize relevant information to PciRoot
PciVirtualConfigMmio: Inspired by PCI configuration space, CrosVM provides 2048 dword virtual registers (8KiB in total) for each PCI device. The guest can use these registers to exchange device-specific information with crosvm. The first 4kB is trapped by crosvm and crosvm supplies these register’s emulation. The second 4KB is mapped into guest directly as shared memory, so when guest access this 4KB, vm exit doesn’t happen. All these virtual registers from all PCI devices locate in a contiguous memory region. The base address of this memory region is provided by an IntObj named VCFG in the ACPI DSDT. Bit 12 is used to select the first trapped page or the second directly mapped page The offset of each register is calculated in the same way as PCIe ECAM; i.e. offset = (bus << 21) | (device << 16) | (function << 13) | (page_select << 12) | (register_index << 2)
PciVirtualConfigMmioSerializable 🔒