Struct devices::irqchip::Apic

pub struct Apic {
    id: u8,
    cycle_length: Duration,
    regs: [u8; 4096],
    mp_state: MPState,
    timer: Box<dyn TimerTrait>,
    timer_length: Option<Duration>,
    last_tick: Instant,
    sipi: Option<Vector>,
    init: bool,
    nmis: u32,
}

Fields

id: u8

cycle_length: Duration

Base duration for the APIC timer. A timer set with initial count = 1 and timer frequency divide = 1 runs for this long.

regs: [u8; 4096]

mp_state: MPState

timer: Box<dyn TimerTrait>

timer_length: Option<Duration>

last_tick: Instant

sipi: Option<Vector>

init: bool

nmis: u32

Implementations

impl Apic

pub fn new(id: u8, timer: Box<dyn TimerTrait>) -> Self

Constructs a new APIC with local APIC ID id.

pub fn frequency() -> u32

Get the Apic frequency in Hz

pub fn id(&self) -> u8

Returns the local APIC ID.

pub fn get_cycle_length(&self) -> Duration

Returns the base duration for the APIC timer. A timer set with initial count = 1 and timer frequency divide = 1 runs for this long.

pub fn get_state(&self) -> LapicState

Returns the state of the APIC registers.

pub fn set_state(&mut self, state: &LapicState)

Sets the state of the APIC registers.

pub fn get_mp_state(&self) -> MPState

Gets the multi-processing state.

pub fn set_mp_state(&mut self, state: &MPState)

Sets the multi-processing state.

fn valid_mmio(offset: u64, data: &[u8]) -> bool

Checks that offset is 16-byte aligned and data is 4 bytes.

pub fn read(&self, offset: u64, data: &mut [u8])

Handles an MMIO read forwarded from the IRQ chip. Reads data from the APIC’s register at offset into data.

pub fn write(&mut self, offset: u64, data: &[u8]) -> Option<ApicBusMsg>

Handles an MMIO write forwarded from the IRQ chip. Writes data into the APIC’s register at offset, optionally returning a command back to the IRQ chip.

pub fn single_dest_fast(dest: &InterruptDestination) -> Option<u8>

If dest specifies a single destination APIC that can be determined quickly without calling match_dest on each APIC, then return the destination APIC ID, otherwise return None.

pub fn match_dest(&self, dest: &InterruptDestination) -> bool

Returns true if this APIC is one of the destinations of the interrupt dest.

pub fn get_processor_priority(&self) -> u8

Returns the processor priority register.

pub fn accept_irq(&mut self, i: &InterruptData)

Enqueues an interrupt to be delivered to this APIC’s vcpu.

fn inject_interrupt(&mut self, clear: bool) -> Option<Vector>

Returns the highest-priority vector in the IRR that has high enough priority to be serviced (i.e., its priority class is greater than the current processor priority class). If clear is true, the IRR bit for that vector is cleared and the ISR bit is set.

fn decode_icr(&mut self) -> Interrupt

Parses data from the Interrupt Command Register into an interrupt.

fn enabled(&self) -> bool

Returns true if the APIC is software-enabled, false if it’s software-disabled.

pub fn set_enabled(&mut self, enable: bool)

Sets or unsets the software enabled bit in the Spurious Int register.

pub fn get_pending_irqs(&mut self, vcpu_ready: bool) -> PendingInterrupts

Gets pending interrupts to be injected into this APIC’s vcpu. The interrupts returned are cleared from the APIC. vcpu_ready indicates if the vcpu is ready to receive fixed interrupts (i.e., if the vcpu’s interrupt window is open, IF flag is set, and the PIC hasn’t already injected an interrupt).

pub fn load_reset_state(&mut self)

Resets the APIC to its initial state. Used for initializing a new APIC and when the vcpu receives an INIT.

pub fn debug_status(&self) -> String

pub fn handle_timer_expiration(&mut self)

Callback to be called by a timer worker when the timer expires.

fn get_reg(&self, offset: usize) -> u32

Returns the first 4 bytes of the register that starts at offset.

fn set_reg(&mut self, offset: usize, val: u32)

Sets the first 4 bytes of the register that starts at offset to val.

fn reg_bit_for_vector(reg: VectorReg, vector: Vector) -> (usize, u8)

Finds the bit for vector in vector bitmap register reg. Returns (index, bitmask) where index is the index of the register byte for vector, and bitmask has one bit set for the vector bit within that byte.

fn set_vector_bit(&mut self, reg: VectorReg, vector: Vector)

fn clear_vector_bit(&mut self, reg: VectorReg, vector: Vector)

fn highest_bit_in_vector(&self, reg: VectorReg) -> Option<Vector>

Returns the vector of the highest bit set in reg.

fn matches_logical_address(&self, dest: u8) -> bool

Returns true if this apic is a possible destination for the logical address dest.

fn get_timer_divide_control(&self) -> u32

fn start_timer(&mut self)

fn clear_timer(&mut self)

fn next_timer_expiration(&self) -> Duration

Returns the duration remaining until the next timer expiration.

Trait Implementations

impl Drop for Apic

fn drop(&mut self)

Executes the destructor for this type.