#[repr(usize)]enum VectorReg {
Isr = 256,
Tmr = 384,
Irr = 512,
}
Expand description
The APIC registers that store interrupt vector bitmaps. Each has 256 bit flags, one for each interrupt vector. The flags are spread across the first 32 bits of each of eight 16-byte APIC register slots.
Variants§
Isr = 256
In-service register. A bit is set for each interrupt vector currently being serviced by the processor.
Tmr = 384
Trigger mode register. Records whether interrupts are edge-triggered (bit is clear) or level-triggered (bit is set).
Irr = 512
Interrupt request register. A bit is set for each interrupt vector received by the APIC but not yet serviced by the processor.
Trait Implementations§
source§impl PartialEq for VectorReg
impl PartialEq for VectorReg
impl Copy for VectorReg
impl Eq for VectorReg
impl StructuralPartialEq for VectorReg
Auto Trait Implementations§
impl RefUnwindSafe for VectorReg
impl Send for VectorReg
impl Sync for VectorReg
impl Unpin for VectorReg
impl UnwindSafe for VectorReg
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
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