Struct devices::pci::pci_configuration::PciConfiguration

pub struct PciConfiguration {
    registers: [u32; 64],
    writable_bits: [u32; 64],
    bar_used: [bool; 7],
    bar_configs: [Option<PciBarConfiguration>; 7],
    last_capability: Option<(usize, usize)>,
    capability_configs: BTreeMap<usize, Box<dyn PciCapConfig>>,
    mmio_mapping: Option<(Arc<Mutex<MemoryMapping>>, usize)>,
}

Contains the configuration space of a PCI node. See the specification. The configuration space is accessed with DWORD reads and writes from the guest.

Fields

registers: [u32; 64]

writable_bits: [u32; 64]

bar_used: [bool; 7]

bar_configs: [Option<PciBarConfiguration>; 7]

last_capability: Option<(usize, usize)>

capability_configs: BTreeMap<usize, Box<dyn PciCapConfig>>

mmio_mapping: Option<(Arc<Mutex<MemoryMapping>>, usize)>

Implementations

impl PciConfiguration

pub fn new( vendor_id: u16, device_id: u16, class_code: PciClassCode, subclass: &dyn PciSubclass, programming_interface: Option<&dyn PciProgrammingInterface>, header_type: PciHeaderType, subsystem_vendor_id: u16, subsystem_id: u16, revision_id: u8 ) -> Self

pub fn read_reg(&self, reg_idx: usize) -> u32

Reads a 32bit register from reg_idx in the register map.

pub fn write_reg( &mut self, reg_idx: usize, offset: u64, data: &[u8] ) -> Option<Box<dyn PciCapConfigWriteResult>>

Writes data to PciConfiguration.registers. reg_idx - index into PciConfiguration.registers. offset - PciConfiguration.registers is in unit of DWord, offset define byte offset in the DWord. data - The data to write.

fn write_dword(&mut self, offset: usize, value: u32)

Writes a 32bit dword to offset. offset must be 32bit aligned.

fn write_word(&mut self, offset: usize, value: u16)

Writes a 16bit word to offset. offset must be 16bit aligned.

fn write_byte(&mut self, offset: usize, value: u8)

Writes a byte to offset.

fn write_byte_internal( &mut self, offset: usize, value: u8, apply_writable_mask: bool )

Writes a byte to offset, optionally enforcing read-only bits.

pub fn set_reg(&mut self, reg_idx: usize, data: u32, mask: u32)

Sets the value of a PciConfiguration register. This should be used when device-internal events require changing the configuration space - as such, the writable bits masks do not apply. reg_idx - index into PciConfiguration.registers. data - The data to write. mask - The mask of which bits to modify.

pub fn add_pci_bar( &mut self, config: PciBarConfiguration ) -> Result<PciBarIndex, Error>

Adds a region specified by config. Configures the specified BAR(s) to report this region and size to the guest kernel. Enforces a few constraints (i.e, region size must be power of two, register not already used). Returns ‘None’ on failure all, Some(BarIndex) on success.

pub fn get_bars(&self) -> PciBarIter<'_>

Returns an iterator of the currently configured base address registers.

pub fn get_bar_configuration( &self, bar_num: usize ) -> Option<PciBarConfiguration>

Returns the configuration of a base address register, if present.

pub fn get_bar_type(&self, bar_num: PciBarIndex) -> Option<PciBarRegionType>

Returns the type of the given BAR region.

pub fn get_bar_addr(&self, bar_num: PciBarIndex) -> u64

Returns the address of the given BAR region.

pub fn set_irq(&mut self, line: u8, pin: PciInterruptPin)

Configures the IRQ line and pin used by this device.

pub fn add_capability( &mut self, cap_data: &dyn PciCapability, cap_config: Option<Box<dyn PciCapConfig>> ) -> Result<(), Error>

Adds the capability cap_data to the list of capabilities. cap_data should include the two-byte PCI capability header (type, next), but not populate it. Correct values will be generated automatically based on cap_data.id().

fn next_dword(offset: usize, len: usize) -> usize

fn do_write(&mut self, reg_idx: usize, value: u32)

pub fn snapshot(&mut self) -> Result<Value>

pub fn restore(&mut self, data: Value) -> Result<()>

pub fn setup_mapping( &mut self, shmem: &SharedMemory, base: usize, len: usize ) -> Result<()>