x86_64/
msr_index.rs

1// Copyright 2017 The ChromiumOS Authors
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5/*
6 * automatically generated by rust-bindgen
7 * From upstream linux msr-index.h at commit:
8 * 806276b7f07a39a1cc3f38bb1ef5c573d4594a38
9 */
10
11pub const MSR_EFER: ::std::os::raw::c_uint = 0xc0000080;
12pub const MSR_STAR: ::std::os::raw::c_uint = 0xc0000081;
13pub const MSR_LSTAR: ::std::os::raw::c_uint = 0xc0000082;
14pub const MSR_CSTAR: ::std::os::raw::c_uint = 0xc0000083;
15pub const MSR_SYSCALL_MASK: ::std::os::raw::c_uint = 0xc0000084;
16pub const MSR_FS_BASE: ::std::os::raw::c_uint = 0xc0000100;
17pub const MSR_GS_BASE: ::std::os::raw::c_uint = 0xc0000101;
18pub const MSR_KERNEL_GS_BASE: ::std::os::raw::c_uint = 0xc0000102;
19pub const MSR_TSC_AUX: ::std::os::raw::c_uint = 0xc0000103;
20pub const _EFER_SCE: ::std::os::raw::c_uint = 0x00000000;
21pub const _EFER_LME: ::std::os::raw::c_uint = 0x00000008;
22pub const _EFER_LMA: ::std::os::raw::c_uint = 0x0000000a;
23pub const _EFER_NX: ::std::os::raw::c_uint = 0x0000000b;
24pub const _EFER_SVME: ::std::os::raw::c_uint = 0x0000000c;
25pub const _EFER_LMSLE: ::std::os::raw::c_uint = 0x0000000d;
26pub const _EFER_FFXSR: ::std::os::raw::c_uint = 0x0000000e;
27pub const EFER_SCE: ::std::os::raw::c_uint = 0x00000001;
28pub const EFER_LME: ::std::os::raw::c_uint = 0x00000100;
29pub const EFER_LMA: ::std::os::raw::c_uint = 0x00000400;
30pub const EFER_NX: ::std::os::raw::c_uint = 0x00000800;
31pub const EFER_SVME: ::std::os::raw::c_uint = 0x00001000;
32pub const EFER_LMSLE: ::std::os::raw::c_uint = 0x00002000;
33pub const EFER_FFXSR: ::std::os::raw::c_uint = 0x00004000;
34pub const MSR_PPIN_CTL: ::std::os::raw::c_uint = 0x0000004e;
35pub const MSR_PPIN: ::std::os::raw::c_uint = 0x0000004f;
36pub const MSR_IA32_PERFCTR0: ::std::os::raw::c_uint = 0x000000c1;
37pub const MSR_IA32_PERFCTR1: ::std::os::raw::c_uint = 0x000000c2;
38pub const MSR_FSB_FREQ: ::std::os::raw::c_uint = 0x000000cd;
39pub const MSR_PLATFORM_INFO: ::std::os::raw::c_uint = 0x000000ce;
40pub const MSR_PKG_CST_CONFIG_CONTROL: ::std::os::raw::c_uint = 0x000000e2;
41pub const NHM_C3_AUTO_DEMOTE: ::std::os::raw::c_uint = 0x02000000;
42pub const NHM_C1_AUTO_DEMOTE: ::std::os::raw::c_uint = 0x04000000;
43pub const ATM_LNC_C6_AUTO_DEMOTE: ::std::os::raw::c_uint = 0x02000000;
44pub const SNB_C1_AUTO_UNDEMOTE: ::std::os::raw::c_uint = 0x08000000;
45pub const SNB_C3_AUTO_UNDEMOTE: ::std::os::raw::c_uint = 0x10000000;
46pub const MSR_MTRRcap: ::std::os::raw::c_uint = 0x000000fe;
47pub const MSR_IA32_BBL_CR_CTL: ::std::os::raw::c_uint = 0x00000119;
48pub const MSR_IA32_BBL_CR_CTL3: ::std::os::raw::c_uint = 0x0000011e;
49pub const MSR_IA32_SYSENTER_CS: ::std::os::raw::c_uint = 0x00000174;
50pub const MSR_IA32_SYSENTER_ESP: ::std::os::raw::c_uint = 0x00000175;
51pub const MSR_IA32_SYSENTER_EIP: ::std::os::raw::c_uint = 0x00000176;
52pub const MSR_IA32_MCG_CAP: ::std::os::raw::c_uint = 0x00000179;
53pub const MSR_IA32_MCG_STATUS: ::std::os::raw::c_uint = 0x0000017a;
54pub const MSR_IA32_MCG_CTL: ::std::os::raw::c_uint = 0x0000017b;
55pub const MSR_IA32_MCG_EXT_CTL: ::std::os::raw::c_uint = 0x000004d0;
56pub const MSR_OFFCORE_RSP_0: ::std::os::raw::c_uint = 0x000001a6;
57pub const MSR_OFFCORE_RSP_1: ::std::os::raw::c_uint = 0x000001a7;
58pub const MSR_TURBO_RATIO_LIMIT: ::std::os::raw::c_uint = 0x000001ad;
59pub const MSR_TURBO_RATIO_LIMIT1: ::std::os::raw::c_uint = 0x000001ae;
60pub const MSR_TURBO_RATIO_LIMIT2: ::std::os::raw::c_uint = 0x000001af;
61pub const MSR_LBR_SELECT: ::std::os::raw::c_uint = 0x000001c8;
62pub const MSR_LBR_TOS: ::std::os::raw::c_uint = 0x000001c9;
63pub const MSR_LBR_NHM_FROM: ::std::os::raw::c_uint = 0x00000680;
64pub const MSR_LBR_NHM_TO: ::std::os::raw::c_uint = 0x000006c0;
65pub const MSR_LBR_CORE_FROM: ::std::os::raw::c_uint = 0x00000040;
66pub const MSR_LBR_CORE_TO: ::std::os::raw::c_uint = 0x00000060;
67pub const MSR_LBR_INFO_0: ::std::os::raw::c_uint = 0x00000dc0;
68pub const LBR_INFO_CYCLES: ::std::os::raw::c_uint = 0x0000ffff;
69pub const MSR_IA32_PEBS_ENABLE: ::std::os::raw::c_uint = 0x000003f1;
70pub const MSR_IA32_DS_AREA: ::std::os::raw::c_uint = 0x00000600;
71pub const MSR_IA32_PERF_CAPABILITIES: ::std::os::raw::c_uint = 0x00000345;
72pub const MSR_PEBS_LD_LAT_THRESHOLD: ::std::os::raw::c_uint = 0x000003f6;
73pub const MSR_IA32_RTIT_CTL: ::std::os::raw::c_uint = 0x00000570;
74pub const MSR_IA32_RTIT_STATUS: ::std::os::raw::c_uint = 0x00000571;
75pub const MSR_IA32_RTIT_ADDR0_A: ::std::os::raw::c_uint = 0x00000580;
76pub const MSR_IA32_RTIT_ADDR0_B: ::std::os::raw::c_uint = 0x00000581;
77pub const MSR_IA32_RTIT_ADDR1_A: ::std::os::raw::c_uint = 0x00000582;
78pub const MSR_IA32_RTIT_ADDR1_B: ::std::os::raw::c_uint = 0x00000583;
79pub const MSR_IA32_RTIT_ADDR2_A: ::std::os::raw::c_uint = 0x00000584;
80pub const MSR_IA32_RTIT_ADDR2_B: ::std::os::raw::c_uint = 0x00000585;
81pub const MSR_IA32_RTIT_ADDR3_A: ::std::os::raw::c_uint = 0x00000586;
82pub const MSR_IA32_RTIT_ADDR3_B: ::std::os::raw::c_uint = 0x00000587;
83pub const MSR_IA32_RTIT_CR3_MATCH: ::std::os::raw::c_uint = 0x00000572;
84pub const MSR_IA32_RTIT_OUTPUT_BASE: ::std::os::raw::c_uint = 0x00000560;
85pub const MSR_IA32_RTIT_OUTPUT_MASK: ::std::os::raw::c_uint = 0x00000561;
86pub const MSR_MTRRfix64K_00000: ::std::os::raw::c_uint = 0x00000250;
87pub const MSR_MTRRfix16K_80000: ::std::os::raw::c_uint = 0x00000258;
88pub const MSR_MTRRfix16K_A0000: ::std::os::raw::c_uint = 0x00000259;
89pub const MSR_MTRRfix4K_C0000: ::std::os::raw::c_uint = 0x00000268;
90pub const MSR_MTRRfix4K_C8000: ::std::os::raw::c_uint = 0x00000269;
91pub const MSR_MTRRfix4K_D0000: ::std::os::raw::c_uint = 0x0000026a;
92pub const MSR_MTRRfix4K_D8000: ::std::os::raw::c_uint = 0x0000026b;
93pub const MSR_MTRRfix4K_E0000: ::std::os::raw::c_uint = 0x0000026c;
94pub const MSR_MTRRfix4K_E8000: ::std::os::raw::c_uint = 0x0000026d;
95pub const MSR_MTRRfix4K_F0000: ::std::os::raw::c_uint = 0x0000026e;
96pub const MSR_MTRRfix4K_F8000: ::std::os::raw::c_uint = 0x0000026f;
97pub const MSR_MTRRdefType: ::std::os::raw::c_uint = 0x000002ff;
98pub const MSR_IA32_CR_PAT: ::std::os::raw::c_uint = 0x00000277;
99pub const MSR_IA32_DEBUGCTLMSR: ::std::os::raw::c_uint = 0x000001d9;
100pub const MSR_IA32_LASTBRANCHFROMIP: ::std::os::raw::c_uint = 0x000001db;
101pub const MSR_IA32_LASTBRANCHTOIP: ::std::os::raw::c_uint = 0x000001dc;
102pub const MSR_IA32_LASTINTFROMIP: ::std::os::raw::c_uint = 0x000001dd;
103pub const MSR_IA32_LASTINTTOIP: ::std::os::raw::c_uint = 0x000001de;
104pub const DEBUGCTLMSR_LBR: ::std::os::raw::c_uint = 0x00000001;
105pub const DEBUGCTLMSR_BTF: ::std::os::raw::c_uint = 0x00000002;
106pub const DEBUGCTLMSR_TR: ::std::os::raw::c_uint = 0x00000040;
107pub const DEBUGCTLMSR_BTS: ::std::os::raw::c_uint = 0x00000080;
108pub const DEBUGCTLMSR_BTINT: ::std::os::raw::c_uint = 0x00000100;
109pub const DEBUGCTLMSR_BTS_OFF_OS: ::std::os::raw::c_uint = 0x00000200;
110pub const DEBUGCTLMSR_BTS_OFF_USR: ::std::os::raw::c_uint = 0x00000400;
111pub const DEBUGCTLMSR_FREEZE_LBRS_ON_PMI: ::std::os::raw::c_uint = 0x00000800;
112pub const MSR_PEBS_FRONTEND: ::std::os::raw::c_uint = 0x000003f7;
113pub const MSR_IA32_POWER_CTL: ::std::os::raw::c_uint = 0x000001fc;
114pub const MSR_IA32_MC0_CTL: ::std::os::raw::c_uint = 0x00000400;
115pub const MSR_IA32_MC0_STATUS: ::std::os::raw::c_uint = 0x00000401;
116pub const MSR_IA32_MC0_ADDR: ::std::os::raw::c_uint = 0x00000402;
117pub const MSR_IA32_MC0_MISC: ::std::os::raw::c_uint = 0x00000403;
118pub const MSR_PKG_C3_RESIDENCY: ::std::os::raw::c_uint = 0x000003f8;
119pub const MSR_PKG_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003f9;
120pub const MSR_ATOM_PKG_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003fa;
121pub const MSR_PKG_C7_RESIDENCY: ::std::os::raw::c_uint = 0x000003fa;
122pub const MSR_CORE_C3_RESIDENCY: ::std::os::raw::c_uint = 0x000003fc;
123pub const MSR_CORE_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003fd;
124pub const MSR_CORE_C7_RESIDENCY: ::std::os::raw::c_uint = 0x000003fe;
125pub const MSR_KNL_CORE_C6_RESIDENCY: ::std::os::raw::c_uint = 0x000003ff;
126pub const MSR_PKG_C2_RESIDENCY: ::std::os::raw::c_uint = 0x0000060d;
127pub const MSR_PKG_C8_RESIDENCY: ::std::os::raw::c_uint = 0x00000630;
128pub const MSR_PKG_C9_RESIDENCY: ::std::os::raw::c_uint = 0x00000631;
129pub const MSR_PKG_C10_RESIDENCY: ::std::os::raw::c_uint = 0x00000632;
130pub const MSR_PKGC3_IRTL: ::std::os::raw::c_uint = 0x0000060a;
131pub const MSR_PKGC6_IRTL: ::std::os::raw::c_uint = 0x0000060b;
132pub const MSR_PKGC7_IRTL: ::std::os::raw::c_uint = 0x0000060c;
133pub const MSR_PKGC8_IRTL: ::std::os::raw::c_uint = 0x00000633;
134pub const MSR_PKGC9_IRTL: ::std::os::raw::c_uint = 0x00000634;
135pub const MSR_PKGC10_IRTL: ::std::os::raw::c_uint = 0x00000635;
136pub const MSR_RAPL_POWER_UNIT: ::std::os::raw::c_uint = 0x00000606;
137pub const MSR_PKG_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000610;
138pub const MSR_PKG_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000611;
139pub const MSR_PKG_PERF_STATUS: ::std::os::raw::c_uint = 0x00000613;
140pub const MSR_PKG_POWER_INFO: ::std::os::raw::c_uint = 0x00000614;
141pub const MSR_DRAM_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000618;
142pub const MSR_DRAM_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000619;
143pub const MSR_DRAM_PERF_STATUS: ::std::os::raw::c_uint = 0x0000061b;
144pub const MSR_DRAM_POWER_INFO: ::std::os::raw::c_uint = 0x0000061c;
145pub const MSR_PP0_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000638;
146pub const MSR_PP0_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000639;
147pub const MSR_PP0_POLICY: ::std::os::raw::c_uint = 0x0000063a;
148pub const MSR_PP0_PERF_STATUS: ::std::os::raw::c_uint = 0x0000063b;
149pub const MSR_PP1_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000640;
150pub const MSR_PP1_ENERGY_STATUS: ::std::os::raw::c_uint = 0x00000641;
151pub const MSR_PP1_POLICY: ::std::os::raw::c_uint = 0x00000642;
152pub const MSR_CONFIG_TDP_NOMINAL: ::std::os::raw::c_uint = 0x00000648;
153pub const MSR_CONFIG_TDP_LEVEL_1: ::std::os::raw::c_uint = 0x00000649;
154pub const MSR_CONFIG_TDP_LEVEL_2: ::std::os::raw::c_uint = 0x0000064a;
155pub const MSR_CONFIG_TDP_CONTROL: ::std::os::raw::c_uint = 0x0000064b;
156pub const MSR_TURBO_ACTIVATION_RATIO: ::std::os::raw::c_uint = 0x0000064c;
157pub const MSR_PLATFORM_ENERGY_STATUS: ::std::os::raw::c_uint = 0x0000064d;
158pub const MSR_PKG_WEIGHTED_CORE_C0_RES: ::std::os::raw::c_uint = 0x00000658;
159pub const MSR_PKG_ANY_CORE_C0_RES: ::std::os::raw::c_uint = 0x00000659;
160pub const MSR_PKG_ANY_GFXE_C0_RES: ::std::os::raw::c_uint = 0x0000065a;
161pub const MSR_PKG_BOTH_CORE_GFXE_C0_RES: ::std::os::raw::c_uint = 0x0000065b;
162pub const MSR_CORE_C1_RES: ::std::os::raw::c_uint = 0x00000660;
163pub const MSR_MODULE_C6_RES_MS: ::std::os::raw::c_uint = 0x00000664;
164pub const MSR_CC6_DEMOTION_POLICY_CONFIG: ::std::os::raw::c_uint = 0x00000668;
165pub const MSR_MC6_DEMOTION_POLICY_CONFIG: ::std::os::raw::c_uint = 0x00000669;
166pub const MSR_ATOM_CORE_RATIOS: ::std::os::raw::c_uint = 0x0000066a;
167pub const MSR_ATOM_CORE_VIDS: ::std::os::raw::c_uint = 0x0000066b;
168pub const MSR_ATOM_CORE_TURBO_RATIOS: ::std::os::raw::c_uint = 0x0000066c;
169pub const MSR_ATOM_CORE_TURBO_VIDS: ::std::os::raw::c_uint = 0x0000066d;
170pub const MSR_CORE_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x00000690;
171pub const MSR_GFX_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x000006b0;
172pub const MSR_RING_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x000006b1;
173pub const MSR_PPERF: ::std::os::raw::c_uint = 0x0000064e;
174pub const MSR_PERF_LIMIT_REASONS: ::std::os::raw::c_uint = 0x0000064f;
175pub const MSR_PM_ENABLE: ::std::os::raw::c_uint = 0x00000770;
176pub const MSR_HWP_CAPABILITIES: ::std::os::raw::c_uint = 0x00000771;
177pub const MSR_HWP_REQUEST_PKG: ::std::os::raw::c_uint = 0x00000772;
178pub const MSR_HWP_INTERRUPT: ::std::os::raw::c_uint = 0x00000773;
179pub const MSR_HWP_REQUEST: ::std::os::raw::c_uint = 0x00000774;
180pub const MSR_HWP_STATUS: ::std::os::raw::c_uint = 0x00000777;
181pub const HWP_BASE_BIT: ::std::os::raw::c_uint = 0x00000080;
182pub const HWP_NOTIFICATIONS_BIT: ::std::os::raw::c_uint = 0x00000100;
183pub const HWP_ACTIVITY_WINDOW_BIT: ::std::os::raw::c_uint = 0x00000200;
184pub const HWP_ENERGY_PERF_PREFERENCE_BIT: ::std::os::raw::c_uint = 0x00000400;
185pub const HWP_PACKAGE_LEVEL_REQUEST_BIT: ::std::os::raw::c_uint = 0x00000800;
186pub const MSR_AMD64_MC0_MASK: ::std::os::raw::c_uint = 0xc0010044;
187pub const MSR_IA32_MC0_CTL2: ::std::os::raw::c_uint = 0x00000280;
188pub const MSR_P6_PERFCTR0: ::std::os::raw::c_uint = 0x000000c1;
189pub const MSR_P6_PERFCTR1: ::std::os::raw::c_uint = 0x000000c2;
190pub const MSR_P6_EVNTSEL0: ::std::os::raw::c_uint = 0x00000186;
191pub const MSR_P6_EVNTSEL1: ::std::os::raw::c_uint = 0x00000187;
192pub const MSR_KNC_PERFCTR0: ::std::os::raw::c_uint = 0x00000020;
193pub const MSR_KNC_PERFCTR1: ::std::os::raw::c_uint = 0x00000021;
194pub const MSR_KNC_EVNTSEL0: ::std::os::raw::c_uint = 0x00000028;
195pub const MSR_KNC_EVNTSEL1: ::std::os::raw::c_uint = 0x00000029;
196pub const MSR_IA32_PMC0: ::std::os::raw::c_uint = 0x000004c1;
197pub const MSR_AMD64_PATCH_LEVEL: ::std::os::raw::c_uint = 0x0000008b;
198pub const MSR_AMD64_TSC_RATIO: ::std::os::raw::c_uint = 0xc0000104;
199pub const MSR_AMD64_NB_CFG: ::std::os::raw::c_uint = 0xc001001f;
200pub const MSR_AMD64_PATCH_LOADER: ::std::os::raw::c_uint = 0xc0010020;
201pub const MSR_AMD64_OSVW_ID_LENGTH: ::std::os::raw::c_uint = 0xc0010140;
202pub const MSR_AMD64_OSVW_STATUS: ::std::os::raw::c_uint = 0xc0010141;
203pub const MSR_AMD64_LS_CFG: ::std::os::raw::c_uint = 0xc0011020;
204pub const MSR_AMD64_DC_CFG: ::std::os::raw::c_uint = 0xc0011022;
205pub const MSR_AMD64_BU_CFG2: ::std::os::raw::c_uint = 0xc001102a;
206pub const MSR_AMD64_IBSFETCHCTL: ::std::os::raw::c_uint = 0xc0011030;
207pub const MSR_AMD64_IBSFETCHLINAD: ::std::os::raw::c_uint = 0xc0011031;
208pub const MSR_AMD64_IBSFETCHPHYSAD: ::std::os::raw::c_uint = 0xc0011032;
209pub const MSR_AMD64_IBSFETCH_REG_COUNT: ::std::os::raw::c_uint = 0x00000003;
210pub const MSR_AMD64_IBSFETCH_REG_MASK: ::std::os::raw::c_uint = 0x00000007;
211pub const MSR_AMD64_IBSOPCTL: ::std::os::raw::c_uint = 0xc0011033;
212pub const MSR_AMD64_IBSOPRIP: ::std::os::raw::c_uint = 0xc0011034;
213pub const MSR_AMD64_IBSOPDATA: ::std::os::raw::c_uint = 0xc0011035;
214pub const MSR_AMD64_IBSOPDATA2: ::std::os::raw::c_uint = 0xc0011036;
215pub const MSR_AMD64_IBSOPDATA3: ::std::os::raw::c_uint = 0xc0011037;
216pub const MSR_AMD64_IBSDCLINAD: ::std::os::raw::c_uint = 0xc0011038;
217pub const MSR_AMD64_IBSDCPHYSAD: ::std::os::raw::c_uint = 0xc0011039;
218pub const MSR_AMD64_IBSOP_REG_COUNT: ::std::os::raw::c_uint = 0x00000007;
219pub const MSR_AMD64_IBSOP_REG_MASK: ::std::os::raw::c_uint = 0x0000007f;
220pub const MSR_AMD64_IBSCTL: ::std::os::raw::c_uint = 0xc001103a;
221pub const MSR_AMD64_IBSBRTARGET: ::std::os::raw::c_uint = 0xc001103b;
222pub const MSR_AMD64_IBSOPDATA4: ::std::os::raw::c_uint = 0xc001103d;
223pub const MSR_AMD64_IBS_REG_COUNT_MAX: ::std::os::raw::c_uint = 0x00000008;
224pub const MSR_F17H_IRPERF: ::std::os::raw::c_uint = 0xc00000e9;
225pub const MSR_F16H_L2I_PERF_CTL: ::std::os::raw::c_uint = 0xc0010230;
226pub const MSR_F16H_L2I_PERF_CTR: ::std::os::raw::c_uint = 0xc0010231;
227pub const MSR_F16H_DR1_ADDR_MASK: ::std::os::raw::c_uint = 0xc0011019;
228pub const MSR_F16H_DR2_ADDR_MASK: ::std::os::raw::c_uint = 0xc001101a;
229pub const MSR_F16H_DR3_ADDR_MASK: ::std::os::raw::c_uint = 0xc001101b;
230pub const MSR_F16H_DR0_ADDR_MASK: ::std::os::raw::c_uint = 0xc0011027;
231pub const MSR_F15H_PERF_CTL: ::std::os::raw::c_uint = 0xc0010200;
232pub const MSR_F15H_PERF_CTR: ::std::os::raw::c_uint = 0xc0010201;
233pub const MSR_F15H_NB_PERF_CTL: ::std::os::raw::c_uint = 0xc0010240;
234pub const MSR_F15H_NB_PERF_CTR: ::std::os::raw::c_uint = 0xc0010241;
235pub const MSR_F15H_PTSC: ::std::os::raw::c_uint = 0xc0010280;
236pub const MSR_F15H_IC_CFG: ::std::os::raw::c_uint = 0xc0011021;
237pub const MSR_FAM10H_MMIO_CONF_BASE: ::std::os::raw::c_uint = 0xc0010058;
238pub const FAM10H_MMIO_CONF_ENABLE: ::std::os::raw::c_uint = 0x00000001;
239pub const FAM10H_MMIO_CONF_BUSRANGE_MASK: ::std::os::raw::c_uint = 0x0000000f;
240pub const FAM10H_MMIO_CONF_BUSRANGE_SHIFT: ::std::os::raw::c_uint = 0x00000002;
241pub const FAM10H_MMIO_CONF_BASE_MASK: ::std::os::raw::c_uint = 0x0fffffff;
242pub const FAM10H_MMIO_CONF_BASE_SHIFT: ::std::os::raw::c_uint = 0x00000014;
243pub const MSR_FAM10H_NODE_ID: ::std::os::raw::c_uint = 0xc001100c;
244pub const MSR_K8_TOP_MEM1: ::std::os::raw::c_uint = 0xc001001a;
245pub const MSR_K8_TOP_MEM2: ::std::os::raw::c_uint = 0xc001001d;
246pub const MSR_K8_SYSCFG: ::std::os::raw::c_uint = 0xc0010010;
247pub const MSR_K8_INT_PENDING_MSG: ::std::os::raw::c_uint = 0xc0010055;
248pub const K8_INTP_C1E_ACTIVE_MASK: ::std::os::raw::c_uint = 0x18000000;
249pub const MSR_K8_TSEG_ADDR: ::std::os::raw::c_uint = 0xc0010112;
250pub const MSR_K8_TSEG_MASK: ::std::os::raw::c_uint = 0xc0010113;
251pub const K8_MTRRFIXRANGE_DRAM_ENABLE: ::std::os::raw::c_uint = 0x00040000;
252pub const K8_MTRRFIXRANGE_DRAM_MODIFY: ::std::os::raw::c_uint = 0x00080000;
253pub const K8_MTRR_RDMEM_WRMEM_MASK: ::std::os::raw::c_uint = 0x18181818;
254pub const MSR_K7_EVNTSEL0: ::std::os::raw::c_uint = 0xc0010000;
255pub const MSR_K7_PERFCTR0: ::std::os::raw::c_uint = 0xc0010004;
256pub const MSR_K7_EVNTSEL1: ::std::os::raw::c_uint = 0xc0010001;
257pub const MSR_K7_PERFCTR1: ::std::os::raw::c_uint = 0xc0010005;
258pub const MSR_K7_EVNTSEL2: ::std::os::raw::c_uint = 0xc0010002;
259pub const MSR_K7_PERFCTR2: ::std::os::raw::c_uint = 0xc0010006;
260pub const MSR_K7_EVNTSEL3: ::std::os::raw::c_uint = 0xc0010003;
261pub const MSR_K7_PERFCTR3: ::std::os::raw::c_uint = 0xc0010007;
262pub const MSR_K7_CLK_CTL: ::std::os::raw::c_uint = 0xc001001b;
263pub const MSR_K7_HWCR: ::std::os::raw::c_uint = 0xc0010015;
264pub const MSR_K7_FID_VID_CTL: ::std::os::raw::c_uint = 0xc0010041;
265pub const MSR_K7_FID_VID_STATUS: ::std::os::raw::c_uint = 0xc0010042;
266pub const MSR_K6_WHCR: ::std::os::raw::c_uint = 0xc0000082;
267pub const MSR_K6_UWCCR: ::std::os::raw::c_uint = 0xc0000085;
268pub const MSR_K6_EPMR: ::std::os::raw::c_uint = 0xc0000086;
269pub const MSR_K6_PSOR: ::std::os::raw::c_uint = 0xc0000087;
270pub const MSR_K6_PFIR: ::std::os::raw::c_uint = 0xc0000088;
271pub const MSR_IDT_FCR1: ::std::os::raw::c_uint = 0x00000107;
272pub const MSR_IDT_FCR2: ::std::os::raw::c_uint = 0x00000108;
273pub const MSR_IDT_FCR3: ::std::os::raw::c_uint = 0x00000109;
274pub const MSR_IDT_FCR4: ::std::os::raw::c_uint = 0x0000010a;
275pub const MSR_IDT_MCR0: ::std::os::raw::c_uint = 0x00000110;
276pub const MSR_IDT_MCR1: ::std::os::raw::c_uint = 0x00000111;
277pub const MSR_IDT_MCR2: ::std::os::raw::c_uint = 0x00000112;
278pub const MSR_IDT_MCR3: ::std::os::raw::c_uint = 0x00000113;
279pub const MSR_IDT_MCR4: ::std::os::raw::c_uint = 0x00000114;
280pub const MSR_IDT_MCR5: ::std::os::raw::c_uint = 0x00000115;
281pub const MSR_IDT_MCR6: ::std::os::raw::c_uint = 0x00000116;
282pub const MSR_IDT_MCR7: ::std::os::raw::c_uint = 0x00000117;
283pub const MSR_IDT_MCR_CTRL: ::std::os::raw::c_uint = 0x00000120;
284pub const MSR_VIA_FCR: ::std::os::raw::c_uint = 0x00001107;
285pub const MSR_VIA_LONGHAUL: ::std::os::raw::c_uint = 0x0000110a;
286pub const MSR_VIA_RNG: ::std::os::raw::c_uint = 0x0000110b;
287pub const MSR_VIA_BCR2: ::std::os::raw::c_uint = 0x00001147;
288pub const MSR_TMTA_LONGRUN_CTRL: ::std::os::raw::c_uint = 0x80868010;
289pub const MSR_TMTA_LONGRUN_FLAGS: ::std::os::raw::c_uint = 0x80868011;
290pub const MSR_TMTA_LRTI_READOUT: ::std::os::raw::c_uint = 0x80868018;
291pub const MSR_TMTA_LRTI_VOLT_MHZ: ::std::os::raw::c_uint = 0x8086801a;
292pub const MSR_IA32_P5_MC_ADDR: ::std::os::raw::c_uint = 0x00000000;
293pub const MSR_IA32_P5_MC_TYPE: ::std::os::raw::c_uint = 0x00000001;
294pub const MSR_IA32_TSC: ::std::os::raw::c_uint = 0x00000010;
295pub const MSR_IA32_PLATFORM_ID: ::std::os::raw::c_uint = 0x00000017;
296pub const MSR_IA32_EBL_CR_POWERON: ::std::os::raw::c_uint = 0x0000002a;
297pub const MSR_EBC_FREQUENCY_ID: ::std::os::raw::c_uint = 0x0000002c;
298pub const MSR_SMI_COUNT: ::std::os::raw::c_uint = 0x00000034;
299pub const MSR_IA32_FEATURE_CONTROL: ::std::os::raw::c_uint = 0x0000003a;
300pub const MSR_IA32_TSC_ADJUST: ::std::os::raw::c_uint = 0x0000003b;
301pub const MSR_IA32_BNDCFGS: ::std::os::raw::c_uint = 0x00000d90;
302pub const MSR_IA32_XSS: ::std::os::raw::c_uint = 0x00000da0;
303pub const FEATURE_CONTROL_LOCKED: ::std::os::raw::c_uint = 0x00000001;
304pub const FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX: ::std::os::raw::c_uint = 0x00000002;
305pub const FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX: ::std::os::raw::c_uint = 0x00000004;
306pub const FEATURE_CONTROL_LMCE: ::std::os::raw::c_uint = 0x00100000;
307pub const MSR_IA32_APICBASE: ::std::os::raw::c_uint = 0x0000001b;
308pub const MSR_IA32_APICBASE_BSP: ::std::os::raw::c_uint = 0x00000100;
309pub const MSR_IA32_APICBASE_ENABLE: ::std::os::raw::c_uint = 0x00000800;
310pub const MSR_IA32_APICBASE_BASE: ::std::os::raw::c_uint = 0xfffff000;
311pub const MSR_IA32_TSCDEADLINE: ::std::os::raw::c_uint = 0x000006e0;
312pub const MSR_IA32_UCODE_WRITE: ::std::os::raw::c_uint = 0x00000079;
313pub const MSR_IA32_UCODE_REV: ::std::os::raw::c_uint = 0x0000008b;
314pub const MSR_IA32_SMM_MONITOR_CTL: ::std::os::raw::c_uint = 0x0000009b;
315pub const MSR_IA32_SMBASE: ::std::os::raw::c_uint = 0x0000009e;
316pub const MSR_IA32_PERF_STATUS: ::std::os::raw::c_uint = 0x00000198;
317pub const MSR_IA32_PERF_CTL: ::std::os::raw::c_uint = 0x00000199;
318pub const INTEL_PERF_CTL_MASK: ::std::os::raw::c_uint = 0x0000ffff;
319pub const MSR_AMD_PSTATE_DEF_BASE: ::std::os::raw::c_uint = 0xc0010064;
320pub const MSR_AMD_PERF_STATUS: ::std::os::raw::c_uint = 0xc0010063;
321pub const MSR_AMD_PERF_CTL: ::std::os::raw::c_uint = 0xc0010062;
322pub const MSR_IA32_MPERF: ::std::os::raw::c_uint = 0x000000e7;
323pub const MSR_IA32_APERF: ::std::os::raw::c_uint = 0x000000e8;
324pub const MSR_IA32_THERM_CONTROL: ::std::os::raw::c_uint = 0x0000019a;
325pub const MSR_IA32_THERM_INTERRUPT: ::std::os::raw::c_uint = 0x0000019b;
326pub const THERM_INT_HIGH_ENABLE: ::std::os::raw::c_uint = 0x00000001;
327pub const THERM_INT_LOW_ENABLE: ::std::os::raw::c_uint = 0x00000002;
328pub const THERM_INT_PLN_ENABLE: ::std::os::raw::c_uint = 0x01000000;
329pub const MSR_IA32_THERM_STATUS: ::std::os::raw::c_uint = 0x0000019c;
330pub const THERM_STATUS_PROCHOT: ::std::os::raw::c_uint = 0x00000001;
331pub const THERM_STATUS_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000400;
332pub const MSR_THERM2_CTL: ::std::os::raw::c_uint = 0x0000019d;
333pub const MSR_THERM2_CTL_TM_SELECT: ::std::os::raw::c_uint = 0x00010000;
334pub const MSR_IA32_MISC_ENABLE: ::std::os::raw::c_uint = 0x000001a0;
335pub const MSR_IA32_TEMPERATURE_TARGET: ::std::os::raw::c_uint = 0x000001a2;
336pub const MSR_MISC_FEATURE_CONTROL: ::std::os::raw::c_uint = 0x000001a4;
337pub const MSR_MISC_PWR_MGMT: ::std::os::raw::c_uint = 0x000001aa;
338pub const MSR_IA32_ENERGY_PERF_BIAS: ::std::os::raw::c_uint = 0x000001b0;
339pub const ENERGY_PERF_BIAS_PERFORMANCE: ::std::os::raw::c_uint = 0x00000000;
340pub const ENERGY_PERF_BIAS_NORMAL: ::std::os::raw::c_uint = 0x00000006;
341pub const ENERGY_PERF_BIAS_POWERSAVE: ::std::os::raw::c_uint = 0x0000000f;
342pub const MSR_IA32_PACKAGE_THERM_STATUS: ::std::os::raw::c_uint = 0x000001b1;
343pub const PACKAGE_THERM_STATUS_PROCHOT: ::std::os::raw::c_uint = 0x00000001;
344pub const PACKAGE_THERM_STATUS_POWER_LIMIT: ::std::os::raw::c_uint = 0x00000400;
345pub const MSR_IA32_PACKAGE_THERM_INTERRUPT: ::std::os::raw::c_uint = 0x000001b2;
346pub const PACKAGE_THERM_INT_HIGH_ENABLE: ::std::os::raw::c_uint = 0x00000001;
347pub const PACKAGE_THERM_INT_LOW_ENABLE: ::std::os::raw::c_uint = 0x00000002;
348pub const PACKAGE_THERM_INT_PLN_ENABLE: ::std::os::raw::c_uint = 0x01000000;
349pub const THERM_INT_THRESHOLD0_ENABLE: ::std::os::raw::c_uint = 0x00008000;
350pub const THERM_SHIFT_THRESHOLD0: ::std::os::raw::c_uint = 0x00000008;
351pub const THERM_MASK_THRESHOLD0: ::std::os::raw::c_uint = 0x00007f00;
352pub const THERM_INT_THRESHOLD1_ENABLE: ::std::os::raw::c_uint = 0x00800000;
353pub const THERM_SHIFT_THRESHOLD1: ::std::os::raw::c_uint = 0x00000010;
354pub const THERM_MASK_THRESHOLD1: ::std::os::raw::c_uint = 0x007f0000;
355pub const THERM_STATUS_THRESHOLD0: ::std::os::raw::c_uint = 0x00000040;
356pub const THERM_LOG_THRESHOLD0: ::std::os::raw::c_uint = 0x00000080;
357pub const THERM_STATUS_THRESHOLD1: ::std::os::raw::c_uint = 0x00000100;
358pub const THERM_LOG_THRESHOLD1: ::std::os::raw::c_uint = 0x00000200;
359pub const MSR_IA32_MISC_ENABLE_FAST_STRING_BIT: ::std::os::raw::c_uint = 0x00000000;
360pub const MSR_IA32_MISC_ENABLE_FAST_STRING: ::std::os::raw::c_uint = 0x00000001;
361pub const MSR_IA32_MISC_ENABLE_TCC_BIT: ::std::os::raw::c_uint = 0x00000001;
362pub const MSR_IA32_MISC_ENABLE_TCC: ::std::os::raw::c_uint = 0x00000002;
363pub const MSR_IA32_MISC_ENABLE_EMON_BIT: ::std::os::raw::c_uint = 0x00000007;
364pub const MSR_IA32_MISC_ENABLE_EMON: ::std::os::raw::c_uint = 0x00000080;
365pub const MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT: ::std::os::raw::c_uint = 0x0000000b;
366pub const MSR_IA32_MISC_ENABLE_BTS_UNAVAIL: ::std::os::raw::c_uint = 0x00000800;
367pub const MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT: ::std::os::raw::c_uint = 0x0000000c;
368pub const MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL: ::std::os::raw::c_uint = 0x00001000;
369pub const MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT: ::std::os::raw::c_uint = 0x00000010;
370pub const MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP: ::std::os::raw::c_uint = 0x00010000;
371pub const MSR_IA32_MISC_ENABLE_MWAIT_BIT: ::std::os::raw::c_uint = 0x00000012;
372pub const MSR_IA32_MISC_ENABLE_MWAIT: ::std::os::raw::c_uint = 0x00040000;
373pub const MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT: ::std::os::raw::c_uint = 0x00000016;
374pub const MSR_IA32_MISC_ENABLE_LIMIT_CPUID: ::std::os::raw::c_uint = 0x00400000;
375pub const MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000017;
376pub const MSR_IA32_MISC_ENABLE_XTPR_DISABLE: ::std::os::raw::c_uint = 0x00800000;
377pub const MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000022;
378pub const MSR_IA32_MISC_ENABLE_XD_DISABLE: ::std::os::raw::c_ulonglong = 0x400000000;
379pub const MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT: ::std::os::raw::c_uint = 0x00000002;
380pub const MSR_IA32_MISC_ENABLE_X87_COMPAT: ::std::os::raw::c_uint = 0x00000004;
381pub const MSR_IA32_MISC_ENABLE_TM1_BIT: ::std::os::raw::c_uint = 0x00000003;
382pub const MSR_IA32_MISC_ENABLE_TM1: ::std::os::raw::c_uint = 0x00000008;
383pub const MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000004;
384pub const MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE: ::std::os::raw::c_uint = 0x00000010;
385pub const MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000006;
386pub const MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE: ::std::os::raw::c_uint = 0x00000040;
387pub const MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT: ::std::os::raw::c_uint = 0x00000008;
388pub const MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK: ::std::os::raw::c_uint = 0x00000100;
389pub const MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000009;
390pub const MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE: ::std::os::raw::c_uint = 0x00000200;
391pub const MSR_IA32_MISC_ENABLE_FERR_BIT: ::std::os::raw::c_uint = 0x0000000a;
392pub const MSR_IA32_MISC_ENABLE_FERR: ::std::os::raw::c_uint = 0x00000400;
393pub const MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT: ::std::os::raw::c_uint = 0x0000000a;
394pub const MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX: ::std::os::raw::c_uint = 0x00000400;
395pub const MSR_IA32_MISC_ENABLE_TM2_BIT: ::std::os::raw::c_uint = 0x0000000d;
396pub const MSR_IA32_MISC_ENABLE_TM2: ::std::os::raw::c_uint = 0x00002000;
397pub const MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000013;
398pub const MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE: ::std::os::raw::c_uint = 0x00080000;
399pub const MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT: ::std::os::raw::c_uint = 0x00000014;
400pub const MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK: ::std::os::raw::c_uint = 0x00100000;
401pub const MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT: ::std::os::raw::c_uint = 0x00000018;
402pub const MSR_IA32_MISC_ENABLE_L1D_CONTEXT: ::std::os::raw::c_uint = 0x01000000;
403pub const MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000025;
404pub const MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE: ::std::os::raw::c_ulonglong = 0x2000000000;
405pub const MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000026;
406pub const MSR_IA32_MISC_ENABLE_TURBO_DISABLE: ::std::os::raw::c_ulonglong = 0x4000000000;
407pub const MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT: ::std::os::raw::c_uint = 0x00000027;
408pub const MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE: ::std::os::raw::c_ulonglong = 0x8000000000;
409pub const MSR_MISC_FEATURE_ENABLES: ::std::os::raw::c_uint = 0x00000140;
410pub const MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT: ::std::os::raw::c_uint = 0x00000001;
411pub const MSR_IA32_TSC_DEADLINE: ::std::os::raw::c_uint = 0x000006e0;
412pub const MSR_IA32_MCG_EAX: ::std::os::raw::c_uint = 0x00000180;
413pub const MSR_IA32_MCG_EBX: ::std::os::raw::c_uint = 0x00000181;
414pub const MSR_IA32_MCG_ECX: ::std::os::raw::c_uint = 0x00000182;
415pub const MSR_IA32_MCG_EDX: ::std::os::raw::c_uint = 0x00000183;
416pub const MSR_IA32_MCG_ESI: ::std::os::raw::c_uint = 0x00000184;
417pub const MSR_IA32_MCG_EDI: ::std::os::raw::c_uint = 0x00000185;
418pub const MSR_IA32_MCG_EBP: ::std::os::raw::c_uint = 0x00000186;
419pub const MSR_IA32_MCG_ESP: ::std::os::raw::c_uint = 0x00000187;
420pub const MSR_IA32_MCG_EFLAGS: ::std::os::raw::c_uint = 0x00000188;
421pub const MSR_IA32_MCG_EIP: ::std::os::raw::c_uint = 0x00000189;
422pub const MSR_IA32_MCG_RESERVED: ::std::os::raw::c_uint = 0x0000018a;
423pub const MSR_P4_BPU_PERFCTR0: ::std::os::raw::c_uint = 0x00000300;
424pub const MSR_P4_BPU_PERFCTR1: ::std::os::raw::c_uint = 0x00000301;
425pub const MSR_P4_BPU_PERFCTR2: ::std::os::raw::c_uint = 0x00000302;
426pub const MSR_P4_BPU_PERFCTR3: ::std::os::raw::c_uint = 0x00000303;
427pub const MSR_P4_MS_PERFCTR0: ::std::os::raw::c_uint = 0x00000304;
428pub const MSR_P4_MS_PERFCTR1: ::std::os::raw::c_uint = 0x00000305;
429pub const MSR_P4_MS_PERFCTR2: ::std::os::raw::c_uint = 0x00000306;
430pub const MSR_P4_MS_PERFCTR3: ::std::os::raw::c_uint = 0x00000307;
431pub const MSR_P4_FLAME_PERFCTR0: ::std::os::raw::c_uint = 0x00000308;
432pub const MSR_P4_FLAME_PERFCTR1: ::std::os::raw::c_uint = 0x00000309;
433pub const MSR_P4_FLAME_PERFCTR2: ::std::os::raw::c_uint = 0x0000030a;
434pub const MSR_P4_FLAME_PERFCTR3: ::std::os::raw::c_uint = 0x0000030b;
435pub const MSR_P4_IQ_PERFCTR0: ::std::os::raw::c_uint = 0x0000030c;
436pub const MSR_P4_IQ_PERFCTR1: ::std::os::raw::c_uint = 0x0000030d;
437pub const MSR_P4_IQ_PERFCTR2: ::std::os::raw::c_uint = 0x0000030e;
438pub const MSR_P4_IQ_PERFCTR3: ::std::os::raw::c_uint = 0x0000030f;
439pub const MSR_P4_IQ_PERFCTR4: ::std::os::raw::c_uint = 0x00000310;
440pub const MSR_P4_IQ_PERFCTR5: ::std::os::raw::c_uint = 0x00000311;
441pub const MSR_P4_BPU_CCCR0: ::std::os::raw::c_uint = 0x00000360;
442pub const MSR_P4_BPU_CCCR1: ::std::os::raw::c_uint = 0x00000361;
443pub const MSR_P4_BPU_CCCR2: ::std::os::raw::c_uint = 0x00000362;
444pub const MSR_P4_BPU_CCCR3: ::std::os::raw::c_uint = 0x00000363;
445pub const MSR_P4_MS_CCCR0: ::std::os::raw::c_uint = 0x00000364;
446pub const MSR_P4_MS_CCCR1: ::std::os::raw::c_uint = 0x00000365;
447pub const MSR_P4_MS_CCCR2: ::std::os::raw::c_uint = 0x00000366;
448pub const MSR_P4_MS_CCCR3: ::std::os::raw::c_uint = 0x00000367;
449pub const MSR_P4_FLAME_CCCR0: ::std::os::raw::c_uint = 0x00000368;
450pub const MSR_P4_FLAME_CCCR1: ::std::os::raw::c_uint = 0x00000369;
451pub const MSR_P4_FLAME_CCCR2: ::std::os::raw::c_uint = 0x0000036a;
452pub const MSR_P4_FLAME_CCCR3: ::std::os::raw::c_uint = 0x0000036b;
453pub const MSR_P4_IQ_CCCR0: ::std::os::raw::c_uint = 0x0000036c;
454pub const MSR_P4_IQ_CCCR1: ::std::os::raw::c_uint = 0x0000036d;
455pub const MSR_P4_IQ_CCCR2: ::std::os::raw::c_uint = 0x0000036e;
456pub const MSR_P4_IQ_CCCR3: ::std::os::raw::c_uint = 0x0000036f;
457pub const MSR_P4_IQ_CCCR4: ::std::os::raw::c_uint = 0x00000370;
458pub const MSR_P4_IQ_CCCR5: ::std::os::raw::c_uint = 0x00000371;
459pub const MSR_P4_ALF_ESCR0: ::std::os::raw::c_uint = 0x000003ca;
460pub const MSR_P4_ALF_ESCR1: ::std::os::raw::c_uint = 0x000003cb;
461pub const MSR_P4_BPU_ESCR0: ::std::os::raw::c_uint = 0x000003b2;
462pub const MSR_P4_BPU_ESCR1: ::std::os::raw::c_uint = 0x000003b3;
463pub const MSR_P4_BSU_ESCR0: ::std::os::raw::c_uint = 0x000003a0;
464pub const MSR_P4_BSU_ESCR1: ::std::os::raw::c_uint = 0x000003a1;
465pub const MSR_P4_CRU_ESCR0: ::std::os::raw::c_uint = 0x000003b8;
466pub const MSR_P4_CRU_ESCR1: ::std::os::raw::c_uint = 0x000003b9;
467pub const MSR_P4_CRU_ESCR2: ::std::os::raw::c_uint = 0x000003cc;
468pub const MSR_P4_CRU_ESCR3: ::std::os::raw::c_uint = 0x000003cd;
469pub const MSR_P4_CRU_ESCR4: ::std::os::raw::c_uint = 0x000003e0;
470pub const MSR_P4_CRU_ESCR5: ::std::os::raw::c_uint = 0x000003e1;
471pub const MSR_P4_DAC_ESCR0: ::std::os::raw::c_uint = 0x000003a8;
472pub const MSR_P4_DAC_ESCR1: ::std::os::raw::c_uint = 0x000003a9;
473pub const MSR_P4_FIRM_ESCR0: ::std::os::raw::c_uint = 0x000003a4;
474pub const MSR_P4_FIRM_ESCR1: ::std::os::raw::c_uint = 0x000003a5;
475pub const MSR_P4_FLAME_ESCR0: ::std::os::raw::c_uint = 0x000003a6;
476pub const MSR_P4_FLAME_ESCR1: ::std::os::raw::c_uint = 0x000003a7;
477pub const MSR_P4_FSB_ESCR0: ::std::os::raw::c_uint = 0x000003a2;
478pub const MSR_P4_FSB_ESCR1: ::std::os::raw::c_uint = 0x000003a3;
479pub const MSR_P4_IQ_ESCR0: ::std::os::raw::c_uint = 0x000003ba;
480pub const MSR_P4_IQ_ESCR1: ::std::os::raw::c_uint = 0x000003bb;
481pub const MSR_P4_IS_ESCR0: ::std::os::raw::c_uint = 0x000003b4;
482pub const MSR_P4_IS_ESCR1: ::std::os::raw::c_uint = 0x000003b5;
483pub const MSR_P4_ITLB_ESCR0: ::std::os::raw::c_uint = 0x000003b6;
484pub const MSR_P4_ITLB_ESCR1: ::std::os::raw::c_uint = 0x000003b7;
485pub const MSR_P4_IX_ESCR0: ::std::os::raw::c_uint = 0x000003c8;
486pub const MSR_P4_IX_ESCR1: ::std::os::raw::c_uint = 0x000003c9;
487pub const MSR_P4_MOB_ESCR0: ::std::os::raw::c_uint = 0x000003aa;
488pub const MSR_P4_MOB_ESCR1: ::std::os::raw::c_uint = 0x000003ab;
489pub const MSR_P4_MS_ESCR0: ::std::os::raw::c_uint = 0x000003c0;
490pub const MSR_P4_MS_ESCR1: ::std::os::raw::c_uint = 0x000003c1;
491pub const MSR_P4_PMH_ESCR0: ::std::os::raw::c_uint = 0x000003ac;
492pub const MSR_P4_PMH_ESCR1: ::std::os::raw::c_uint = 0x000003ad;
493pub const MSR_P4_RAT_ESCR0: ::std::os::raw::c_uint = 0x000003bc;
494pub const MSR_P4_RAT_ESCR1: ::std::os::raw::c_uint = 0x000003bd;
495pub const MSR_P4_SAAT_ESCR0: ::std::os::raw::c_uint = 0x000003ae;
496pub const MSR_P4_SAAT_ESCR1: ::std::os::raw::c_uint = 0x000003af;
497pub const MSR_P4_SSU_ESCR0: ::std::os::raw::c_uint = 0x000003be;
498pub const MSR_P4_SSU_ESCR1: ::std::os::raw::c_uint = 0x000003bf;
499pub const MSR_P4_TBPU_ESCR0: ::std::os::raw::c_uint = 0x000003c2;
500pub const MSR_P4_TBPU_ESCR1: ::std::os::raw::c_uint = 0x000003c3;
501pub const MSR_P4_TC_ESCR0: ::std::os::raw::c_uint = 0x000003c4;
502pub const MSR_P4_TC_ESCR1: ::std::os::raw::c_uint = 0x000003c5;
503pub const MSR_P4_U2L_ESCR0: ::std::os::raw::c_uint = 0x000003b0;
504pub const MSR_P4_U2L_ESCR1: ::std::os::raw::c_uint = 0x000003b1;
505pub const MSR_P4_PEBS_MATRIX_VERT: ::std::os::raw::c_uint = 0x000003f2;
506pub const MSR_CORE_PERF_FIXED_CTR0: ::std::os::raw::c_uint = 0x00000309;
507pub const MSR_CORE_PERF_FIXED_CTR1: ::std::os::raw::c_uint = 0x0000030a;
508pub const MSR_CORE_PERF_FIXED_CTR2: ::std::os::raw::c_uint = 0x0000030b;
509pub const MSR_CORE_PERF_FIXED_CTR_CTRL: ::std::os::raw::c_uint = 0x0000038d;
510pub const MSR_CORE_PERF_GLOBAL_STATUS: ::std::os::raw::c_uint = 0x0000038e;
511pub const MSR_CORE_PERF_GLOBAL_CTRL: ::std::os::raw::c_uint = 0x0000038f;
512pub const MSR_CORE_PERF_GLOBAL_OVF_CTRL: ::std::os::raw::c_uint = 0x00000390;
513pub const MSR_GEODE_BUSCONT_CONF0: ::std::os::raw::c_uint = 0x00001900;
514pub const MSR_IA32_VMX_BASIC: ::std::os::raw::c_uint = 0x00000480;
515pub const MSR_IA32_VMX_PINBASED_CTLS: ::std::os::raw::c_uint = 0x00000481;
516pub const MSR_IA32_VMX_PROCBASED_CTLS: ::std::os::raw::c_uint = 0x00000482;
517pub const MSR_IA32_VMX_EXIT_CTLS: ::std::os::raw::c_uint = 0x00000483;
518pub const MSR_IA32_VMX_ENTRY_CTLS: ::std::os::raw::c_uint = 0x00000484;
519pub const MSR_IA32_VMX_MISC: ::std::os::raw::c_uint = 0x00000485;
520pub const MSR_IA32_VMX_CR0_FIXED0: ::std::os::raw::c_uint = 0x00000486;
521pub const MSR_IA32_VMX_CR0_FIXED1: ::std::os::raw::c_uint = 0x00000487;
522pub const MSR_IA32_VMX_CR4_FIXED0: ::std::os::raw::c_uint = 0x00000488;
523pub const MSR_IA32_VMX_CR4_FIXED1: ::std::os::raw::c_uint = 0x00000489;
524pub const MSR_IA32_VMX_VMCS_ENUM: ::std::os::raw::c_uint = 0x0000048a;
525pub const MSR_IA32_VMX_PROCBASED_CTLS2: ::std::os::raw::c_uint = 0x0000048b;
526pub const MSR_IA32_VMX_EPT_VPID_CAP: ::std::os::raw::c_uint = 0x0000048c;
527pub const MSR_IA32_VMX_TRUE_PINBASED_CTLS: ::std::os::raw::c_uint = 0x0000048d;
528pub const MSR_IA32_VMX_TRUE_PROCBASED_CTLS: ::std::os::raw::c_uint = 0x0000048e;
529pub const MSR_IA32_VMX_TRUE_EXIT_CTLS: ::std::os::raw::c_uint = 0x0000048f;
530pub const MSR_IA32_VMX_TRUE_ENTRY_CTLS: ::std::os::raw::c_uint = 0x00000490;
531pub const MSR_IA32_VMX_VMFUNC: ::std::os::raw::c_uint = 0x00000491;
532pub const VMX_BASIC_VMCS_SIZE_SHIFT: ::std::os::raw::c_uint = 0x00000020;
533pub const VMX_BASIC_TRUE_CTLS: ::std::os::raw::c_ulonglong = 0x80000000000000;
534pub const VMX_BASIC_64: ::std::os::raw::c_ulonglong = 0x1000000000000;
535pub const VMX_BASIC_MEM_TYPE_SHIFT: ::std::os::raw::c_uint = 0x00000032;
536pub const VMX_BASIC_MEM_TYPE_MASK: ::std::os::raw::c_ulonglong = 0x3c000000000000;
537pub const VMX_BASIC_MEM_TYPE_WB: ::std::os::raw::c_uint = 0x00000006;
538pub const VMX_BASIC_INOUT: ::std::os::raw::c_ulonglong = 0x40000000000000;
539pub const MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS: ::std::os::raw::c_uint = 0x20000000;
540pub const MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE: ::std::os::raw::c_uint = 0x0000001f;
541pub const MSR_VM_CR: ::std::os::raw::c_uint = 0xc0010114;
542pub const MSR_VM_IGNNE: ::std::os::raw::c_uint = 0xc0010115;
543pub const MSR_VM_HSAVE_PA: ::std::os::raw::c_uint = 0xc0010117;
x86_64/msr_index.rs

x86_64/
msr_index.rs
