hypervisor/
caps.rs

1// Copyright 2020 The ChromiumOS Authors
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5/// An enumeration of different hypervisor capabilities.
6#[derive(Clone, Copy, Debug, Eq, PartialEq)]
7pub enum HypervisorCap {
8    ImmediateExit,
9    UserMemory,
10    #[cfg(target_arch = "x86_64")]
11    Xcrs,
12    #[cfg(target_arch = "x86_64")]
13    /// CPUID leaf 0x15 is available on some Intel chips and contains the TSC
14    /// frequency, which can be used to calibrate the guest's TSC clocksource;
15    /// however, it is not typically accurate enough (being off by 1-2% is a
16    /// big problem for a clocksource), and inside the guest, calibration by
17    /// other means is not always reliable.
18    ///
19    /// Hypervisors which do not provide the TSC frequency (e.g. via the kvm
20    /// pvclock) or have another suitable calibration source can declare this
21    /// capability, which causes crosvm to substitute a calibrated value in leaf
22    /// 0x15 that will be accurate enough for use in a clocksource.
23    CalibratedTscLeafRequired,
24    // By default, when swiotlb is enabled, crosvm will only specify its size in the device tree
25    // and allow the guest to decide where to allocate the buffer in guest phsyical memory.
26    //
27    // If this capability is declared, then instead crosvm will carve out space at the end of
28    // physical memory and register it as a distinct memory region. Then, both the address and
29    // size will be specified in the device tree. This region will still be reported as part
30    // of the main memory region in the device tree.
31    StaticSwiotlbAllocationRequired,
32    /// Some hypervisors (presently: Gunyah) will configure initial boot-time registers
33    /// for vCPUs without need for CrosVM to specify.
34    ///
35    /// If this capability is declared, then crosvm will not try to initialize vcpu
36    /// registers when creating the VM.
37    HypervisorInitializedBootContext,
38}
39
40/// A capability the `Vm` can possibly expose.
41#[derive(Clone, Copy, Debug, Eq, PartialEq)]
42pub enum VmCap {
43    #[cfg(target_arch = "aarch64")]
44    ArmPmuV3,
45    /// Track dirty pages
46    DirtyLog,
47    /// Paravirtualized clock device
48    PvClock,
49    /// VM can be run in protected mode, where the host does not have access to its memory.
50    Protected,
51    /// VM completes initialization of CPUID at creation time, not required after.
52    EarlyInitCpuid,
53    /// VM can detect the bus lock
54    #[cfg(target_arch = "x86_64")]
55    BusLockDetect,
56    /// Supports read-only memory regions.
57    ReadOnlyMemoryRegion,
58    /// VM can set guest memory cache noncoherent DMA flag
59    MemNoncoherentDma,
60    /// If supported, this VM supports enabling ARM SVE (Scalable Vector Extension)
61    /// by requesting `VcpuFeature::Sve` when calling `VcpuAarch64::init()`.
62    #[cfg(target_arch = "aarch64")]
63    Sve,
64}
hypervisor/caps.rs

hypervisor/
caps.rs
