aarch64_sys_reg/
funcs.rs

1// Copyright 2025 The ChromiumOS Authors
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5//! AArch64 system register range functions.
6//!
7//! This file consists of manually written functions to generate registers that cannot be handled
8//! automatically by the code generator.
9
10#![allow(non_snake_case, non_upper_case_globals)]
11
12use crate::AArch64SysRegId;
13
14const fn bit(val: u8, bit_index: u32) -> u8 {
15    (val >> bit_index) & 1
16}
17
18const fn bits(val: u8, hi_index: u32, lo_index: u32) -> u8 {
19    let mask = 1u8.wrapping_shl(hi_index - lo_index + 1).wrapping_sub(1);
20    (val >> lo_index) & mask
21}
22
23pub const fn AMEVCNTR0n_EL0(m: u8) -> AArch64SysRegId {
24    assert!(m <= 3);
25    let crm = (0b010 << 1) | bit(m, 3);
26    let op2 = bits(m, 2, 0);
27    AArch64SysRegId::new_unchecked(0b11, 0b011, 0b1101, crm, op2)
28}
29
30pub const fn AMEVCNTR1n_EL0(m: u8) -> AArch64SysRegId {
31    assert!(m <= 15);
32    let crm = (0b110 << 1) | bit(m, 3);
33    let op2 = bits(m, 2, 0);
34    AArch64SysRegId::new_unchecked(0b11, 0b011, 0b1101, crm, op2)
35}
36
37pub const fn AMEVCNTVOFF0n_EL2(m: u8) -> AArch64SysRegId {
38    assert!(m <= 15);
39    let crm = (0b100 << 1) | bit(m, 3);
40    let op2 = bits(m, 2, 0);
41    AArch64SysRegId::new_unchecked(0b11, 0b100, 0b1101, crm, op2)
42}
43
44pub const fn AMEVCNTVOFF1n_EL2(m: u8) -> AArch64SysRegId {
45    assert!(m <= 15);
46    let crm = (0b101 << 1) | bit(m, 3);
47    let op2 = bits(m, 2, 0);
48    AArch64SysRegId::new_unchecked(0b11, 0b100, 0b1101, crm, op2)
49}
50
51pub const fn AMEVTYPER0n_EL0(m: u8) -> AArch64SysRegId {
52    assert!(m <= 3);
53    let crm = (0b011 << 1) | bit(m, 3);
54    let op2 = bits(m, 2, 0);
55    AArch64SysRegId::new_unchecked(0b11, 0b011, 0b1101, crm, op2)
56}
57
58pub const fn AMEVTYPER1n_EL0(m: u8) -> AArch64SysRegId {
59    assert!(m <= 15);
60    let crm = (0b111 << 1) | bit(m, 3);
61    let op2 = bits(m, 2, 0);
62    AArch64SysRegId::new_unchecked(0b11, 0b011, 0b1101, crm, op2)
63}
64
65pub const fn BRBINFn_EL1(m: u8) -> AArch64SysRegId {
66    assert!(m <= 31);
67    let crm = bits(m, 3, 0);
68    let op2 = (bit(m, 4) << 2) | 0b00;
69    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b1000, crm, op2)
70}
71
72pub const fn BRBSRCn_EL1(m: u8) -> AArch64SysRegId {
73    assert!(m <= 31);
74    let crm = bits(m, 3, 0);
75    let op2 = (bit(m, 4) << 2) | 0b01;
76    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b1000, crm, op2)
77}
78
79pub const fn BRBTGTn_EL1(m: u8) -> AArch64SysRegId {
80    assert!(m <= 31);
81    let crm = bits(m, 3, 0);
82    let op2 = (bit(m, 4) << 2) | 0b10;
83    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b1000, crm, op2)
84}
85
86pub const fn DBGBCRn_EL1(m: u8) -> AArch64SysRegId {
87    assert!(m <= 15);
88    let crm = bits(m, 3, 0);
89    AArch64SysRegId::new_unchecked(0b10, 0b000, 0b0000, crm, 0b101)
90}
91
92pub const fn DBGBVRn_EL1(m: u8) -> AArch64SysRegId {
93    assert!(m <= 15);
94    let crm = bits(m, 3, 0);
95    AArch64SysRegId::new_unchecked(0b10, 0b000, 0b0000, crm, 0b100)
96}
97
98pub const fn DBGWCRn_EL1(m: u8) -> AArch64SysRegId {
99    assert!(m <= 15);
100    let crm = bits(m, 3, 0);
101    AArch64SysRegId::new_unchecked(0b10, 0b000, 0b0000, crm, 0b111)
102}
103
104pub const fn DBGWVRn_EL1(m: u8) -> AArch64SysRegId {
105    assert!(m <= 15);
106    let crm = bits(m, 3, 0);
107    AArch64SysRegId::new_unchecked(0b10, 0b000, 0b0000, crm, 0b110)
108}
109
110pub const fn ICC_AP0Rn_EL1(m: u8) -> AArch64SysRegId {
111    assert!(m <= 3);
112    let op2 = (0b1 << 2) | bits(m, 1, 0);
113    AArch64SysRegId::new_unchecked(0b11, 0b000, 0b1100, 0b1000, op2)
114}
115
116pub const fn ICC_AP1Rn_EL1(m: u8) -> AArch64SysRegId {
117    assert!(m <= 3);
118    let op2 = (0b0 << 2) | bits(m, 1, 0);
119    AArch64SysRegId::new_unchecked(0b11, 0b000, 0b1100, 0b1001, op2)
120}
121
122pub const fn ICH_AP0Rn_EL2(m: u8) -> AArch64SysRegId {
123    assert!(m <= 3);
124    let op2 = (0b0 << 2) | bits(m, 1, 0);
125    AArch64SysRegId::new_unchecked(0b11, 0b100, 0b1100, 0b1000, op2)
126}
127
128pub const fn ICH_AP1Rn_EL2(m: u8) -> AArch64SysRegId {
129    assert!(m <= 3);
130    let op2 = (0b0 << 2) | bits(m, 1, 0);
131    AArch64SysRegId::new_unchecked(0b11, 0b100, 0b1100, 0b1001, op2)
132}
133
134pub const fn ICH_LRn_EL2(m: u8) -> AArch64SysRegId {
135    assert!(m <= 15);
136    let crm = (0b110 << 1) | bit(m, 3);
137    let op2 = bits(m, 2, 0);
138    AArch64SysRegId::new_unchecked(0b11, 0b100, 0b1100, crm, op2)
139}
140
141pub const fn PMEVCNTRn_EL0(m: u8) -> AArch64SysRegId {
142    assert!(m <= 30);
143    let crm = (0b10 << 2) | bits(m, 4, 3);
144    let op2 = bits(m, 2, 0);
145    AArch64SysRegId::new_unchecked(0b11, 0b011, 0b1110, crm, op2)
146}
147
148pub const fn PMEVCNTSVRn_EL1(m: u8) -> AArch64SysRegId {
149    assert!(m <= 30);
150    let crm = (0b10 << 2) | bits(m, 4, 3);
151    let op2 = bits(m, 2, 0);
152    AArch64SysRegId::new_unchecked(0b10, 0b000, 0b1110, crm, op2)
153}
154
155pub const fn PMEVTYPERn_EL0(m: u8) -> AArch64SysRegId {
156    assert!(m <= 30);
157    let crm = (0b11 << 2) | bits(m, 4, 3);
158    let op2 = bits(m, 2, 0);
159    AArch64SysRegId::new_unchecked(0b11, 0b011, 0b1110, crm, op2)
160}
161
162pub const fn SPMCGCRn_EL1(m: u8) -> AArch64SysRegId {
163    assert!(m <= 1);
164    let op2 = (0b00 << 1) | bit(m, 0);
165    AArch64SysRegId::new_unchecked(0b10, 0b000, 0b1001, 0b1101, op2)
166}
167
168pub const fn SPMEVCNTRn_EL0(m: u8) -> AArch64SysRegId {
169    assert!(m <= 15);
170    let crm = (0b000 << 1) | bit(m, 3);
171    let op2 = bits(m, 2, 0);
172    AArch64SysRegId::new_unchecked(0b10, 0b011, 0b1110, crm, op2)
173}
174
175pub const fn SPMEVFILT2Rn_EL0(m: u8) -> AArch64SysRegId {
176    assert!(m <= 15);
177    let crm = (0b011 << 1) | bit(m, 3);
178    let op2 = bits(m, 2, 0);
179    AArch64SysRegId::new_unchecked(0b10, 0b011, 0b1110, crm, op2)
180}
181
182pub const fn SPMEVFILTRn_EL0(m: u8) -> AArch64SysRegId {
183    assert!(m <= 15);
184    let crm = (0b010 << 1) | bit(m, 3);
185    let op2 = bits(m, 2, 0);
186    AArch64SysRegId::new_unchecked(0b10, 0b011, 0b1110, crm, op2)
187}
188
189pub const fn SPMEVTYPERn_EL0(m: u8) -> AArch64SysRegId {
190    assert!(m <= 15);
191    let crm = (0b001 << 1) | bit(m, 3);
192    let op2 = bits(m, 2, 0);
193    AArch64SysRegId::new_unchecked(0b10, 0b011, 0b1110, crm, op2)
194}
195
196pub const fn TRCACATRn(m: u8) -> AArch64SysRegId {
197    assert!(m <= 15);
198    let crm = (bits(m, 2, 0) << 1) | 0b0;
199    let op2 = (0b01 << 1) | bit(m, 3);
200    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0010, crm, op2)
201}
202
203pub const fn TRCACVRn(m: u8) -> AArch64SysRegId {
204    assert!(m <= 15);
205    let crm = (bits(m, 2, 0) << 1) | 0b0;
206    let op2 = (0b00 << 1) | bit(m, 3);
207    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0010, crm, op2)
208}
209
210pub const fn TRCCIDCVRn(m: u8) -> AArch64SysRegId {
211    assert!(m <= 7);
212    let crm = (bits(m, 2, 0) << 1) | 0b0;
213    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0011, crm, 0b000)
214}
215
216pub const fn TRCCNTCTLRn(m: u8) -> AArch64SysRegId {
217    assert!(m <= 3);
218    let crm = (0b01 << 2) | bits(m, 1, 0);
219    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0000, crm, 0b101)
220}
221
222pub const fn TRCCNTRLDVRn(m: u8) -> AArch64SysRegId {
223    assert!(m <= 3);
224    let crm = (0b00 << 1) | bits(m, 1, 0);
225    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0000, crm, 0b101)
226}
227
228pub const fn TRCCNTVRn(m: u8) -> AArch64SysRegId {
229    assert!(m <= 3);
230    let crm = (0b10 << 2) | bits(m, 1, 0);
231    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0000, crm, 0b101)
232}
233
234pub const fn TRCEXTINSELRn(m: u8) -> AArch64SysRegId {
235    assert!(m <= 3);
236    let crm = (0b10 << 2) | bits(m, 1, 0);
237    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0000, crm, 0b100)
238}
239
240pub const fn TRCIMSPECn(m: u8) -> AArch64SysRegId {
241    assert!(m >= 1 && m <= 7);
242    let crm = (0b0 << 3) | bits(m, 2, 0);
243    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0000, crm, 0b111)
244}
245
246pub const fn TRCRSCTLRn(m: u8) -> AArch64SysRegId {
247    assert!(m >= 2 && m <= 31);
248    let crm = bits(m, 3, 0);
249    let op2 = (0b00 << 1) | bit(m, 4);
250    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0001, crm, op2)
251}
252
253pub const fn TRCSEQEVRn(m: u8) -> AArch64SysRegId {
254    assert!(m <= 2);
255    let crm = (0b00 << 2) | bits(m, 1, 0);
256    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0000, crm, 0b100)
257}
258
259pub const fn TRCSSCCRn(m: u8) -> AArch64SysRegId {
260    assert!(m <= 7);
261    let crm = (0b0 << 3) | bits(m, 2, 0);
262    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0001, crm, 0b010)
263}
264
265pub const fn TRCSSCSRn(m: u8) -> AArch64SysRegId {
266    assert!(m <= 7);
267    let crm = (0b1 << 3) | bits(m, 2, 0);
268    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0001, crm, 0b010)
269}
270
271pub const fn TRCSSPCICRn(m: u8) -> AArch64SysRegId {
272    assert!(m <= 7);
273    let crm = (0b0 << 3) | bits(m, 2, 0);
274    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0001, crm, 0b011)
275}
276
277pub const fn TRCVMIDCVRn(m: u8) -> AArch64SysRegId {
278    assert!(m <= 7);
279    let crm = (bits(m, 2, 0) << 1) | 0b0;
280    AArch64SysRegId::new_unchecked(0b10, 0b001, 0b0011, crm, 0b001)
281}
aarch64_sys_reg/funcs.rs

aarch64_sys_reg/
funcs.rs
