fn create_pcie_root_port(
host_pcie_rp: Vec<HostPcieRootPortParameters>,
sys_allocator: &mut SystemAllocator,
irq_control_tubes: &mut Vec<Tube>,
control_tubes: &mut Vec<TaggedControlTube>,
devices: &mut Vec<(Box<dyn BusDeviceObj>, Option<Minijail>)>,
hp_vec: &mut Vec<(u8, Arc<Mutex<dyn HotPlugBus>>)>,
hp_endpoints_ranges: &mut Vec<RangeInclusive<u32>>,
gpe_notify_devs: &mut Vec<(u32, Arc<Mutex<dyn GpeNotify>>)>,
pme_notify_devs: &mut Vec<(u8, Arc<Mutex<dyn PmeNotify>>)>
) -> Result<()>